1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, such as a gate array, suited for few-of-a kind production in which a wide variety of products are produced in a small quantity for each kind.
2. Prior Art
A process of manufacturing a semiconductor integrated circuit is roughly divided into a diffusion process for forming elements, such as transistors and resistors, on a semiconductor wafer, and a wiring or metallizing process for forming a wiring pattern for connecting these elements with each other. Gate arrays are manufactured by employing the same diffusion process regardless of different kinds of products, and then effecting the wiring process that differs from one product to another so as to produce each kind of product. Namely, in order to manufacture individual kinds of gate arrays, semiconductor wafers (base wafers), each having a multiplicity of transistors disposed thereon, are preliminarily prepared and stored, and, when a certain kind of product is ordered, a wiring pattern required for this kind is formed on the base wafer, so as to provide a semiconductor wafer on which are formed circuits corresponding to the desired kind of product.
The base wafer is divided into a multiplicity of chips that constitute a gate-array device. Although the arrangement of the chips varies depending upon the kind of the product, many gate-array chips are divided into an internal core area and a peripheral area. The internal core area is an area in a which a multiplicity of transistors are arranged in matrix, and the transistors in this area are used to provide a circuit for the desired kind of product, for example, a decoding circuit when a decoding LSI is produced as the desired product. Recent advances in the technology of manufacturing semiconductor devices have enabled a great number of fine or minute transistors to be incorporated in one chip, which leads to the development of a gate array having an internal core area consisting of several tens of thousands of transistors. The peripheral area, on the other hand, is an area that surrounds the internal core area, and transistors in this peripheral area are used to provide input and output circuits for receiving and transmitting signals between the circuit constituted by the transistors in the internal core area and an external device or devices located outside the gate array.
To enable the gate array to perform high-speed operations, the transistors constituting the internal core area need to have increased driving force, which requires an increase in the size (e.g., channel width in the case of a MOS transistor) of each of the transistors. If the size of each transistor is increased, however, the size of the internal core area is accordingly increased, resulting in an increase in the cost per chip. There is also a limit to the manufacturing technology for increasing the chip size. Further, if the driving force of each transistor is increased, the current flowing upon switching of the transistor increases, thereby causing problems such as increased power consumption and reduced lifetime of the wiring. In view of these situations, most of large-scale gate arrays are currently designed by taking account of an average load per gate in a general digital circuit, so that the internal core area consists of transistors having the minimum size required for driving such a load.
The input and output circuits constituted by the transistors of the peripheral area, on the other hand, function to transmit output signals to an external device, and transmit input signals from the external device to respective points of the internal core area; therefore, these transistors are required to produce large driving force. To this end, a general gate array is constructed such that a sufficiently large number or size of transistors are provided in the peripheral area.
Where a large-scale circuit is provided by the gate array, the circuit may be designed such that loads collectively forming a large load are driven by a common control signal. One example is the case where numerous flip-flops are driven by a common clock signal. In this case, a wiring system for transmitting the clock signal involves a large load capacity including the capacity of the wiring itself, as well as the input capacity (gate capacity) of clock terminals of the numerous flip-flops.
If no measures are taken to deal with such a large load capacity, the rise time and fall time of waves of the clock signal or the like which propagate through the wiring system may be extremely prolonged, or the delay time may be extremely increased, thereby possibly causing troubles in the operating timing of the circuit or deterioration of the electric performance (such as operating frequency). In some circuits, a large skew should not arise in clock signals supplied to the respective flip-flops, and a suitable means or device is needed for preventing occurrence of this situation. Where such a large load is to be driven in a conventional gate array, therefore, a plurality of transistors in the internal core area are connected in parallel with each other to provide a driver having a large driving force, and clock signals or the like are supplied to respective points in the circuit through this driver.
Since each of the transistors in the internal core area of the gate array generally has only a small driving force as described above, a considerably large number of transistors need to be used to provide a driver having a large driving force. In the case where the gate array provides a large-scale circuit that inherently requires a large number of transistors, however, it may be impossible to prepare the transistors for providing the driver through which the clock signals are transmitted.